In my role as an independent advisor to industry users of high performance computing, I recently helped to coordinate a private gathering of leading industry users of HPC – no HPC centers, or vendors, just the users of HPC in industry meeting as peers. One key topic we discussed was things that might significantly change how industry deploys and uses high performance computing, what I refer to as “HPC disruptors.”
The upcoming battle between AMD’s “Rome” server CPU and Intel’s “Ice Lake” Xeon scalable processor promises to be an interesting matchup. But this time around, AMD could have an advantage it has never had before.
The competition between the US, China, and Japan to field the first exascale supercomputer looks a lot closer than it did a couple of years ago. But the real significance of the narrowing schedules reflects a shift in technology preferences and a trend toward domestic control of HPC hardware.
The European Processor Initiative (EPI), an ambitious program to develop a pair of chips for domestic supercomputers, is poised to change the way Europe does HPC. And although the work is still very much in its early stages, it looks like the Europeans have selected their preferred processor architectures: Arm and RISC-V.
Researchers at the Great Western 4 (GW4) Alliance have benchmarked the Cavium ThunderX2 processor that will soon power the Isambard supercomputer. But the most significant advantage of the Arm processor may have nothing to do with performance numbers.
The International Supercomputing Conference (ISC18) kicked off Monday in Frankfurt, Germany, with Maria Girone, CTO of CERN openlab delivering the opening keynote address. She explained how CERN’s needs will drive exascale computation and data science innovation in the future.
The TOP500 list is an intensely valuable tool for the HPC community, tracking aggregate trends over 25 years. However, a few observers have noted that recent publications of the TOP500 list have many duplicate entries, often at anonymous sites.