By: Michael Feldman
Intel has come up with a multi-chip module containing a Xeon Skylake processor integrated with an Arria 10 field programmable gate array (FPGA).
Intel made the announcement on its IT Peer Network in a blog posted by Jennifer Huffstetler, vice president and general manager of data center product management. She says the new product consists of a Xeon Scalable Processor 6138P (Gold) processor hooked up to an Arria 10 GX 1150 FPGA on the same package. The chips converse with one another over the Ultra Path Interconnect (UPI) bus, providing a cache-coherent coupling between the two.
The rationale for putting both chips into same socket is to provide a much tighter coupling between the CPU and FPGA than you would get with a discrete PCIe-attached accelerator. Besides the much faster speed and lower latency of UPI compared to PCIe, the bus enables both chips to share data in memory or cache without the overhead of copies or DMA transfers.
The Arria GX 1150 is at the high end of Arria line, with 1.5 million logic elements and DSP blocks capable of delivering 1.366 single-precision teraflops (although its Xeon companion is going to provide a lot more than that in the flops department). This particular FPGA isn’t equipped with an ARM processor, which is present in some of the other Arria SKUs. But given that it’s hooked up to a rather large and powerful CPU, the ARM component would be rather redundant.
According to Huffstetler, this is the first instance of a Xeon integrated with an FPGA in a cache-coherent fashion. In 2016, Intel had a similar Broadwell Xeon-FPGA package, but apparently that never made it into an official product. In this just-announced Skylake version, the hardware is available now, but is only shipping to select customers.
One of those customers could be Paderborn University, in Germany. Back in September 2017, we reported the university would host an HPC cluster equipped with integrated Xeon-FPGA components. As far as we know, that cluster has yet to be deployed, so it would make sense if they were just waiting for Intel to deliver the hardware. Microsoft is another possible early customer, given the company’s devotion to FPGAs for machine learning and network acceleration in its Azure cloud.
Besides HPC, machine learning, and network acceleration, the hybrid processors could also be used for things like data encryption, image processing, media streaming. Huffstetler mentioned that the product is compatible with Open Virtual Switch (OVS), a framework for supporting virtual network switching. According to tests performed by Intel, running OVS on the new Xeon-FGPA delivers a 3.2x throughput improvement with half the latency, compared to running the same software on Xeon-only gear. Fujitsu plans to deliver systems based on the new Xeon-FPGA package and Intel’s OVS reference design.
Intel is also planning to introduce a discrete FPGA with a fast high-bandwidth interconnect that provides coherency. The discrete setup would make it possible to support more powerful FPGAS, such as Stratix devices, but in a more tightly coupled manner. Although no details were forthcoming about the underlying technology that would make this possible, it’s likely they’ll be using UPI in some fashion to support such a capability. No word on when this product will be launched.
Image: Front view of Xeon-Arria module. Source: Intel