Paderborn University Will Offer Intel CPU-FPGA Cluster for Researchers

Sept. 22, 2017

By: Michael Feldman

Paderborn University, in Germany, has announced it has been selected to host an Intel cluster, powered by Intel Xeon CPUs and Arria 10 FPGAs.

If you’ve never heard of Paderborn, that’s because it’s a relatively modest-sized university, located in a relatively modest-sized city of the same name. The institution enrolled just 20,000 students this year, but its Paderborn Center for Parallel Computing (PC2) is engaged in some cutting-edge research that makes it notable in the field of HPC. One area of interest is energy-efficient supercomputing, which, according the PC2 website, has an emphasis on “Field-Programmable Gate Arrays (FPGAs) and Manycore architectures.”

Currently, the center is working on FPGA-accelerated applications in the areas of theoretical physics, material sciences and machine learning. Researchers there are also looking into new domain-specific programming approaches that will make it easier for developers to create applications for these notoriously hard-to-program devices.

All the PC2 research projects are funded externally, and in this instance, the center's benefactor is Intel. It’s not clear if the cluster is being donated by the chipmaker, but this is likely the case, inasmuch as PC2 was “selected” by Intel. In any case, it’s certainly in the company’s interest to foster such research to help build software and expertise around data center use cases for Altera silicon.

The research effort will be targeted at applications where FPGAs have proven to be especially adept at, namely machine learning, data encryption, compression, image processing and video-stream processing. The platform may also be used to research computing systems more generally, especially with regard to “new approaches of integrating CPUs with accelerators at the software and hardware level.”

Hardware-wise, the cluster will consist of server nodes that connect Xeon processors with Arria 10 FPGAs via the QuickPath point-to-point interconnect. The QuickPath hookup avoids the relatively slow PCIe bus used for typical accelerator setups, while also enabling NUMA access for the Altera chips. That should not only allow applications to execute faster, but also make it easier to program those same applications in the first place.

It was just two years ago when CEO Brian Krzanich predicted that up to a third of all cloud computing nodes will be equipped with FPGAs by 2020. That is not likely to happen without the Intel goosing the ecosystem, and this partnership with Paderborn is one of the ways to do that. To that end, researchers inside or outside of Germany can get access to the PC2 cluster by applying to Intel’s Hardware Accelerator Research Program.

“We are looking forward to collaborate with Intel and other members of the Hardware Accelerator Research Program on using FPGA acceleration for emerging HPC and data center workloads,” said Dr. Tobias Kenter, senior researcher and FPGA expert at the Paderborn Center for Parallel Computing. “By provisioning access to the system to a large number of researchers, we are also gathering experience in how to manage systems with FPGA accelerators in a multi-user setting and for handling parallel applications that use multiple servers with FPGAs. This experience is crucial for deploying systems with FPGAs at scale”