By: Michael Feldman
IBM and its partners have developed a novel technology to build 5nm chips, based on silicon nanosheet transistors. Compared to 10nm chips using FinFET transistors, the new technology promises to deliver a 40 percent performance increase, a 75 percent power savings, or some combination of the two.
5nm silicon nanosheet transistors. Credit: IBM
Dr. Huiming Bu, Director of Silicon Integration and Device Research at IBM Research says the approach involves placing the nanosheets in horizontal layers during chip fabrication. “The change from today’s vertical fin architecture to horizontal layers of silicon opened a fourth gate on the transistor that enabled superior electrical signals to pass through and between other transistors on a chip,” Dr. Bu told TOP500 News.
Scientists at IBM Research and its partner SUNY Polytechnic Institute (Colleges of Nanoscale Science and Engineering’s NanoTech Complex) have been working on nanosheet semiconductors in the lab for more than 10 years. But this week’s announcement appears to put the technology on a glide path to commercialization. According to researchers, this is the first time anyone has demonstrated the feasibility of building chips with these nanosheets that will outperform comparable devices built with FinFET technology.
The 5nm chips will employ the same Extreme Ultraviolet (EUV) lithography used for IBM’s 7nm test node chips that the company unveiled in 2015. That technology would deliver 20 billion transistors on a chip, while this new nanosheet approach would increase that to 30 billion.
According to the announcement, the technology also provides an extra benefit. Researchers have found a way to use EUV technology to adjust the width of the nanosheets within a single manufacturing process or chip design. The practical effect of this technique is described as follows:
“This adjustability permits the fine-tuning of performance and power for specific circuits – something not possible with today’s FinFET transistor architecture production, which is limited by its current-carrying fin height. Therefore, while FinFET chips can scale to 5nm, simply reducing the amount of space between fins does not provide increased current flow for additional performance.”
FinFET, short for Fin Field Effect Transistor, is the 3D semiconductor technology Intel began using in commercial chips in 2012, and adopted over the following couple of years by GlobalFoundries and TSMC, among others. Most chip manufacturers plan to use some version of FinFET through the 7nm node. But as the transistor pitch shrinks, taller and thinner fin structures are needed, which makes their manufacture increasingly difficult.
But if all goes as planned, Samsung and Globalfoundaries will be able ditch FinFET and move to nanosheet technology for the 5nm node. As IBM alliance partners, both of these chipmakers will have full access to this technology, since they share patents associated with the nanosheet transistor structure and fabrication.
Chip wafer with 5nm silicon nanosheet transistors. Credit: Connie Zhou
Keep in mind that this initial work represents a feasibility demonstration only. Mass manufacturing of nanosheet transistors could take place within a few years, but would depend upon moving these techniques into a production environment.
This latest development is likely to reignite arguments about the viability of Moore’s Law. But the more immediate goal of shrinking transistor sizes down to 5nm – whether it happens at a Moore’s Law rate or not – at least now has what appears to be a viable path. Moreover, Dr. Bu says they forsee a way for nanosheet transistors to scale beyond 5nm, perhaps using different materials.
The economics of building nanosheet fabs still has to be worked out. Intel says it will spend $7 billion to build its 7nm fab in Arizona, while GlobalFoundaries says it will shell out “several billion” for new tools to update its Malta, New York facility for 7nm production. It’s hard to imagine a 5nm facility based on a novel technology would be less expensive than either of those.
Nevertheless, the escalation in computing demand is making some of the economic arguments against continued transistor shrinkage irrelevant. Even a $10 or $20 billion fab could be a viable investment, given the insatiable appetite for computing from areas like artificial intelligence, virtual reality, the internet of things (IoT) and mobile devices, not to mention supercomputing. At the same time, energy for computing is becoming more expensive, both in operating costs and from the perspective of environment impact. Given that, anything demonstrating 40 percent better performance or 75 percent better energy efficiency is likely to find its way into the market.
Details of the technology will be presented at the 2017 Symposia on VLSI Technology and Circuits conference being held this week in Kyoto, Japan.