By: Michael Feldman
Moore’s Law, the engine that has driven the electronics industry for the past 50 years, is running on fumes. But DARPA, the US Defense Advanced Project Agency, is looking to refill the gas tank with new research initiatives, backed by a $216 million investment.
That investment is being funded under something called the Electronics Resurgence Initiative (ERI), a program being run out of the agency’s Microsystems Technology Office (MTO). Although the MTO has its hands in a number of research programs looking to advance electronics technology, the ERI is specifically aimed at workarounds for Moore’s Law. Currently there is $141 million dedicated to the ERI work in FY18, and last week DARPA allocated an additional $75 million.
The DoD has every right to be concerned about the dwindling prospects for Moore’s Law. Not only is it getting more technically difficult to reduce the size of transistors with conventional semiconductor technology, but the cost of doing so is escalating rapidly. Today’s newest fabs cost several billion dollars to build and that number will rise as transistor geometries get smaller. That means you need increasing chip volume to make construction of such facilities economically feasible. And this has made it even more problematic for the small-volume, high-performance chips that the defense sector relies on for everything from supercomputers to jet aircraft defense systems. “The current trajectory is straining commercial and defense developments,” said MTO director Bill Chappell.
ERI is aimed at three main areas: materials and integration, circuit design, and system architecture, spread out over six new programs. For the purpose of this article, we’re going to focus on the first one, material and integration, since this is the one aimed most closely on building a new foundation for electronics scaling that could pick up where Moore’s Law left off. There are two new programs in this area, the Three Dimensional Monolithic System-on-a-Chip (3DSoC) program, and the Foundations Required for Novel Compute (FRANC) program.
Taking them in order, the 3DSoC, as you may have surmised from the name, is focused on developing 3D chips, thus adding a third dimension to scalability. The program’s mission is summarized thusly:
The goal of the 3DSoC program is to develop the 3D technology required to build logic, memory and I/O on a single die while improving the performance by >50X when compared with 2D 7nm technology. 3DSoC seeks to leverage current industrial and university research in monolithic 3D processes and propel research in the areas of 3DSoC design tools and novel architectures that can be utilized to build highly efficient computation systems.
The main advantage of 3D chips is that they can significantly reduce data access bottlenecks between the logic, memory, and I/O. As is pointed out in the 3DSoC solicitation, for typical deep learning applications, 80 to 90 percent of execution time is spent accessing memory, while only 10 to 20 percent is spent computing. And that’s for a state-of-the-art deep learning accelerator that has been optimized for bandwidth-intensive applications. According to DARPA, the numbers would be even more skewed for a general-purpose processor.
Placing memory and logic chips in the same stack means that you can achieve bandwidths as high as 40 terabytes per second, which is about 100 times faster than what can currently be achieved with the best 2D chips and memory systems. In fact, a 50-fold performance improvement can be demonstrated with simulations of deep learning application when comparing 90nm 3D chips with 7nm 2D chips. That performance improvement jumps an additional 10-fold or so when you use 7nm 3D chips. The added bandwidth, courtesy of the 3D design, offers a huge advantage on these data-intensive codes.
The 3DSoC effort involves coming up with EDA tools and fabrication processes that can be used to manufacture these devices, and then being able to demonstrate high-yield production of such chips for the DoD. The program will run in three phases for a total of 42 months, and is scheduled to end in 2021.
The second materials and integration program, FRANC, sounds even more ambitious. Instead of relying on the traditional semiconductor technology and von Neumann architecture, as is the case for the 3DSoC program, FRANC is aimed at non-von Neumann designs and new types of materials. Its goals are summarized as follows:
The purpose of the FRANC program is to provide the foundation for new materials technology and new integration approaches to be exploited in pursuit of novel compute architectures. The program aims to develop alternate compute topologies that change the compute paradigm from discrete memory and processing to architectures that enable processing to happen where the data is stored with structures that diverge dramatically from conventional digital logic processors, thus allowing for more dramatic gains in compute performance while minimizing the challenges associated with vertical integration.
Examples of this include processors that incorporate memory, and vice versa, as well as logic components that are optimized for NP-hard problems, advanced power provisioning methods, and new types of memory designs. A couple of areas the solicitation recommends looking at is non-volatile memories (beyond NAND and even the newer ReRAM), photonic componentry, and 2.5D integration. The completed designs must offer performance improvements of 10x over current state-of-the-art processors on problems of interest to the DoD. While this effort is designed first and foremost to advance defense electronics, DARPA recognizes that any resulting technology will also be of interest to manufacturers of personal computing and IoT devices.
FRANC will be take place in parallel with the 3DSoC effort, and is scheduled to run for 48 months. At the end of the program, a functioning prototype is expected to be delivered. Both programs are holding “Proposer Days” this month, where interested researchers can gather more information. DARPA has not indicated when the funding will be awarded, but given the FY18 start date for these programs, we can expect the agency to announce its selections within the next several months.