By: TOP500 Team

Code modernization is one of those buzzwords that is becoming widely accepted despite its ambiguity. The term is used to describe the optimization of existing and new community and commercial codes to take advantage of the manycore systems with their highly parallel architectures that are coming online. 

But, as a national lab director recently pointed out, the term also implies that existing applications written for serial machines are outdated and headed for the scrap heap of fusty, obsolete algorithms. Nothing could be further from the truth. There are untold numbers of existing applications that will never outgrow their usefulness. When run on the new architectures, these applications could simply run faster in serial mode although other challenges like data parallelism might get in their way.

Other mathematical models, algorithms and their implementation will benefit from extensive code modification in order to use the new manycore architectures efficiently, including pre-exascale class machines. So code modernization, code modification or code optimization – take your pick – refers generally to on-going efforts to continually evaluate and optimize both existing and new applications as new, highly parallel systems are introduced into both the labs and the enterprise.

A good example is the U.S. Department of Energy allocation of $200 million for the Argonne Leadership Computing Facility (ALCF) to acquire a next-generation supercomputer known as Aurora. This advanced machine will be deployed in 2018. With a peak performance of 180 petaflops, Aurora is well on the path to exascale. Designed and being built using the Intel® Scalable System Framework, the supercomputer will include third generation Intel® Xeon Phi™ processors code name Knights Hill as well as the company’s next generation Intel® Omni-Path Architecture, a leading edge, high speed fabric. Also part of the package are a powerful layered memory architecture and Intel® Enterprise Edition for Lustre* Software, advanced file system storage and software.

Although Aurora is slated for deployment in 2018, code modernization efforts are already well underway using intermediate systems that are part of the same architectural family. Collaboration with science teams through the Early Science Program (ESP) are in the first phase targeting Intel Xeon Phi processors code name Knights Landing based systems. A second phase of the ESP starts in fall of 2016 for the Aurora architecture. As proven through previous programs at the ALCF, this approach accelerates application readiness and provides valuable lessons learned even before the system is generally available. In order to facilitate the process, computational scientists at ALCF are taking a number of steps including:

• Making more efficient use of nodes – Most of Aurora’s speed increase will be made possible by more powerful nodes.  Applications running on these nodes will have to be modified to use the nodes efficiently.
• More efficient vectorization from SIMD units – To use the SIMD vector units in each core, code developers will have to organize their data movement and structure to get maximum efficiency from these units.
• Better use of memory architecture – One of the features of these advanced machines are a variety of memories with different speeds operating within each node. Managing memory allocation is essential for eliciting top performance, a task that is just in its infancy.
• Handling variability in traffic because of network shortcuts built into these future systems. When internode communications links are shared by different jobs, I/O, and OS tasks, communications times will vary between nodes of a single job. This calls for a far more flexible approach to communications times as compared to today’s applications that rely on a consistent communications time to get optimum performance.

Over at NERSC similar preparations are underway to ready applications to run on the Cori supercomputer, which features Intel Xeon Phi processors code name Knights Landing. Over 5,000 users and 700 projects will be transitioned from NERSC’s Edison supercomputer powered by Intel Xeon processors (formerly known as Ivy Bridge) to the Intel Xeon Phi processor code name Knights Landing –based Cori system. Part of that effort is the code modernization of applications so that they provide good MPI scaling, exploit vectorization, and use OpenMP or a comparable threading model to increase thread parallelism by an order of magnitude to over 240 threads per processor.

To make all this happen, 20 application teams are working closely with Intel and Cray to modify their applications to run efficiently on the Intel Xeon Phi processor nodes. NERSC tends to select applications that already have a large parallel runtime sections. These codes are amenable to thread and vector optimization. However, other applications that rely heavily on serial processing can be difficult to modify – code modernization in these cases might take years to accomplish.

In the meantime, in the interval between now and the deployment of Cori, applications team members are using hardware proxies to run lots of threads and vectorization on Intel Xeon Phi processors. They are also exploring the implications of taking full advantage of node-based mixed memory platforms.

Other programs, such as the Early Science Projects or their equivalent at several of the labs, are helping to prepare selected engineering and scientific projects to run on early versions of the supercomputers and/or simulators. The idea is to have these projects parallelized and vectorized to a point where they will be able to run efficiently on the actual production versions of computers like Aurora when they are deployed at labs such as ALCF and NERSC.

Intel’s Modern Code program provides training, tools, libraries and other resources that will help equip organizations to tackle their code modernization efforts.

Whether it’s called code modernization, code modification, code optimization or some other catchy buzzword, these various activities at the country’s top labs are moving high performance computing to a new level as we head toward exascale.