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Viewing posts from May, 2016

Cavium Makes Noise with New ThunderX2 ARM Chip

Cavium has launched its latest ARM server processor, the ThunderX2, a second-generation SoC aimed at the same datacenter workloads that are currently dominated by Intel’s Xeon CPUs. The new chip is designed to go head-to-head with those Xeons, while at the same time get out in front of the 64-bit ARM competition from Applied Micro, Broadcom, and others.

The “Smart Factory” of the Fourth Industrial Revolution: An Interview with Fraunhofer’s Thomas Bauernhansl

The fourth industrial revolution is upon us. At least that’s the view of German business leaders and the government, who are blazing a new path in manufacturing with the Industrie 4.0 initiative. As in the third industrial revolution, information technology will be key enabler. But what comes next will intimately link manufacturing with the internet, the ubiquitous digital platform of the 21st century, along with other advanced computer technologies. The result will be what is sometimes referred to as the smart factory.

Cray's Newest Analytics Supercomputer and India's Home-Grown HPC

Addison and Michael analyze the week's big HPC news.

Baidu Accelerates Self-Driving Car Effort with GPU-Powered HPC

Google isn’t the only hyperscale company that is developing autonomous vehicles. Chinese internet giant Baidu is also aggressively pursuing this nascent market, albeit with less public fanfare than its American counterpart. This week though, more about the project’s inner workings was revealed when Inspur announced that its GPU-accelerated servers had been selected by Baidu as a platform for the company’s deep learning image recognition system.

New Cache Coherent Interconnect Takes Aim at Datacenter Accelerators

If you happen to think there aren’t enough interconnect standards for accelerators in the world, then you’ll be happy to know that one more has been added to the heap. The new technology, known as the Cache Coherent Interconnect for Acceleration (CCIX), is being crafted as an open standard and aims to provide a high performance, cache coherent data link between processor hosts and coprocessor accelerators.