Earth-Simulator

The Earth Simulator was developed for Japan Aerospace Exploration Agency, Japan Atomic Energy Research Institute, and Japan Marine Science and Technology Center. The system is Located at the Earth Simulator Center (ESC) in Kanazawa-ku (ward), Yokohama-shi, Japan.

It is able to run holistic simulations of global climate in both the atmosphere and the oceans down to a resolution of 10 km. Its performance on the HPL benchmark is 35.86 TFLOPS.

Built by NEC, the Earth Simulator is based on their SX-6 architecture. It consists of 640 nodes with eight vector processors and 16 gigabytes of computer memory at each node, for a total of 5120 processors and 10 terabytes of memory.

Construction started in October 1999, was completed by February 2002, and the site officially opened on March 11, 2002. The project cost 7.2 billion yen.

Earth Simulator's capacity was surpassed by IBM's Blue Gene/L prototype on September 29, 2004.

The ESC has several special features that help to protect the computer from natural disasters or occurrences. A wire nest hangs over the building which helps to protect from lightning. The nest itself uses high-voltage shielded cables to release lightning current into the ground. A special light propagation system utilizes halogen lamps, installed outside of the shielded machine room walls, to prevent any magnetic interference from reaching the computers. The building is constructed on a seismic isolation system, composed of rubber supports, that protect the building during earthquakes.

System Configuration

The ES is a highly parallel vector supercomputer system of the distributed-memory type, and consisted of 640 processor nodes (PNs) connected by 640x640 single-stage crossbar switches. Each PN is a system with a shared memory, consisting of 8 vector-type arithmetic processors (APs), a 16-GB main memory system (MS), a remote access control unit (RCU), and an I/O processor. The peak performance of each AP is 8Gflops. The ES as a whole thus consists of 5120 APs with 10 TB of main memory and the theoretical performance of 40Tflop.

Construction of Arithmetic Processor (AP)

Each AP consists of a 4-way super-scalar unit (SU), a vector unit (VU), and main memory access control unit on a single LSI chip. The AP operates at a clock frequency of 500MHz with some circuits operating at 1GHz. Each SU is a super-scalar processor with 64KB instruction caches, 64KB data caches, and 128 general-purpose scalar registers. Branch prediction, data prefetching and out-of-order instruction execution are all employed. Each VU has 72 vector registers, each of which has 256 vector elements, along with 8 sets of six different types of vector pipelines: addition/shifting, multiplication, division, logical operations, masking, and load/store. The same type of vector pipelines works together by a single vector instruction and pipelines of different types can operate concurrently. The VU and SU support the IEEE 754 floating-point data format.

1 Chip LSI : 8Gflops

• 0.15Еm CMOS
• 8Layers copper interconnection
• 20.79mm x 20.79mm
• 60 million transistors
• 5185 pins
• Clock Cycle: 500MHz(1GHz)
• Power Consumption: 140W (Typ.)

Processor Node (PN)

The overall MS is divided into 2048 banks and the sequence of bank numbers corresponds to increasing addresses of locations in memory. Therefore, the peak throughput is obtained by accessing contiguous data which are assigned to locations in increasing order of memory address.