June 3, 2016
The National Science Foundation (NSF) is spending $30 million on the second iteration of Stampede supercomputer, which will provide 18 petaflops worth of compute to tens of thousands of scientists and researchers across the US. Named after its predecessor, Stampede 2, will double the FLOP-count of the original system, which cost $27.5 million when it came online in 2013. As with the original Stampede, the new machine will be housed at the Texas Advanced Computing Center (TACC) at The University of Texas at Austin (UT Austin).
The double-up in FLOPS is courtesy of the Intel’s “Knights Landing” Xeon Phi processors, which began shipping earlier this year. The first system employed the older “Knights Corner” generation, a 61-core coprocessor built on 22nm technology, which delivered just over a teraflop of peak double precession performance. The new Knight Landing chips house 72 cores, are manufactured with a 14nm (3D transistor) technology, and promise over 3 teraflops per processor. If the system relied entirely on them, that would mean Stampede 2 would require close to 6,000 such chips, but according to the TACC announcement, some of the nodes will use “next generation” Xeon CPUs as well.
Besides the big bump in FLOPS, Stampede 2 will double memory, storage capacity, and system bandwidth. The latter will benefit from Intel’s new Omni-Path interconnect, a fabric technology whose first iteration will deliver 100 Gbps of inter-server bandwidth. The original Stampede relied on FDR 56Gbps InfiniBand as the system fabric.
The memory technology that will be incorporated into the supercomputer will be as important as the processor upgrades, and for memory-bound applications, even more so. The new Xeon Phi package will have the multi-channel DRAM (MCDRAM) modules, which deliver about four times the bandwidth of DDR4 memory. As such, it can act as a massive third level cache store, very fast conventional memory, or some combination of the two.
Even more exotic is the 3D XPoint non-volatile memory, which will be used in some of the Stampede nodes deployed in the last phase of the deployment. The technology was unveiled by Intel and Micron in 2015, but has yet to be seen in the wild. It promises faster speeds than flash NAND memory, with cheaper prices than regular DRAM.
The deployment timeline remains somewhat of a mystery, which probably means Intel is not sure when it will be able to deliver all the various componentry. They likely have already begun to assemble the system and will continue the build-out through 2017. Dell is the system vendor, with Seagate as the storage provider.