About Remedies, Losses and Farewells

Andreas Stiller

(Translation of the German original in c't by Marcel Sieslack)

Once a year, at the International Electron Devices Meeting (IEDM), the experts of the craft meet to report on the advancements in transistor, memory and manufacturing technology. Intel is struggling with the C1-step of its newest processors and AMD miscounts.

New materials are supposed to enhance the mobility of the charge carriers in PMOS and NMOS by a factor of 30, said head of production, Mark Bohr, at the IEDM in Washington D.C. In the future, field effect transistors are expected to be able to run on voltages of down to 0.3 V and thus consume 10-times less energy, and with nanowires it would be possible to create even smaller transistors.

Also IBM talked about such carbon nanotube transistors, as well as about the so-called racetrack memory technology with nanowires. First prototypes, manufactured in standard CMOS technology, are still comparatively big, but IBM hopes to step up the memory density by two dimensions in comparison to hard discs while undercutting the power consumption and costs of flash technology. Also IMEC and Samsung showed off new non-volatile memories: resistive random access memory (PRAM) with a circuit time of only 10 ns.

Micron has teamed up with IBM to bring three-dimensional memory blocks, called memory cubes (HMC), to the market that can transfer up to 128 GB per second. With the help of IBM, the HM cubes are supposed to reach marked-readiness in the second half of 2013 already, instead of sometime around 2014/2015, as Micron had projected so far. The server manufacturers are planning already ...

However, it was a small start-up from California that managed to draw the most attention. SuVolta has developed a deeply depleted channel transistor technology that runs on a mere 0.425 V, works with current CMOS technology and, at equal performance, only consumes half as much power as conventional transistors. Fujitsu has already produced the first promising test chips with DDC transistors.

Meanwhile, Intel has arrived at 14 nm, first test chips are running in the labs – lots of high hopes for the future, but first, the postponed Sandy Bridge EP Xeons in current 32-nm technology will have to roll out. Anyone who has a copy of Intel's Processor Sighting Report #452856, which you can only get under a non-disclosure agreement (NDA), has known for a while now that one of the 91 known bugs in the C1 stepping of the processors for the LGA2011 socket causes problems in connection with the I/O virtualization VT-d. But now, this bug is also officially listed in the specification update for the recently released Sandy Bridge-E (Core i7-3960x and i7-39xxK), under BS90.

There is an easy remedy: Do without VT-d altogether or at least refrain from using the affected function (queued invalidation). But that's not necessarily the appropriate solution for servers, which probably is one of the main reasons why the Sandy Bridge-EP Xeons haven't been launched yet. The VT-d bug is supposed to have been fixed in the current C2-stepping now. For desktop systems, VT-d should rarely be of importance, but still, the new i7 processors for LGA2011 have apparently been shipped rather reluctantly. "Due to limited supply", it reads in Intel's product change notification (PCN 111178-00), the intention is to quickly switch to processors with C2-stepping.

The deeply depleted channel technology from SuVolta changes the characteristic of the transistors by over 0.2 V and thus reduces power consumption by 50 percent or more.

Losses

In the meantime, competitor AMD released an odd specification update of a different kind. Apparently, the responsible intern slightly miscalculated when counting the number of transistors on the Bulldozer chip Zambezi, ending up with 800 million too many, should happens. Now, instead of 2 billion, there are supposed to be only 1.2 billion. And so, the performance-per-transistor consideration in comparison to the 4-core Sandy Bridge with its 1 billion transistors now leads to somewhat reasonable values – with the former number this comparison suggested that AMD's new processor was awfully inefficient.

With only 1.2 billion transistors the Bulldozer die seems rather large at 315 mm², the Sandy Bridge die only measures 216 mm². However, AMD talks about "active transistors" – apparently, the automatic design tool must have added lots of passive transistors. Or maybe the chip has lots of additional functions and units, officially planned only for later generations, for test purposes. Such secret test features have always been present on Intel's chips, too. For instance, the first Pentium P5 prototypes already featured physical address extension (PAE), but it was disabled for the final production version. In the first user's manual it was still documented by mistake, but was quickly removed then. Some years later, the Pentium Pro finally came with PAE. And the first Pentium 4 Willamette was internally equipped with hyperthreading already, while Foster and Northwood, which officially featured it, arrived two years later. So who knows what's lying dormant in the Bulldozer's lost 800 million transistors?

AMD announced another loss: The Torrenza bites the dust. The concept, announced in the summer of 2006, was meant to link coprocessors more closely to the main processor. Part of it was the Torrenza Innovation Socket, which was supposed to give the coprocessor a cache-coherent access to the shared main memory, similar to a CPU, via hypertransport. There hardly was any hardware for it, though.

In an interview with the journalist Anna Filatova of Xbit Labs, AMD's director of ISV Relationship, Neal Robison, now said that they have bid farewell to this concept and were now favoring APU's that are directly integrated into the socket with the CPU. Also, it's seems certain that AMD will go for integrated PCIe 3.0 for its CPUs in the not-too-distant future; Intel's LGA2011 processors will already come equipped with it. And the PCIe train is moving fast: At the start of December, the PCI SIG already announced PCIe 4.0 for 2014/15, which is supposed to be twice as fast as PCIe 3, running with 16 GT/s per lane.

PCIe 3 is expected to soon find its way into the discrete high-end graphics and GPGPU cards from AMD and Nvidia - but not Intel, whose planned coprocessor card Knights Corner is said to come equipped with the leisurely PCIe 2. It's rather droll, Intel has the compatible CPUs, the others have the GPUs.