About Rocky Creeks and New Shores
(Translation of the German original in c't 25/09 by Marcel Sieslack)
Sun’s Rock is dead; long live Rock Creek, Intel’s new experimental processor. Intel hopes for EU research funds – and for a friendlier new EU competition commissioner. AMD is going to talk about new deactivatable cores at the ISSCC conference.
No, it’s not meant for productive application – Intel’s new processor Rock Creek with the impressive official name “Single-chip Cloud Computer” (SCC). Rather, its purpose is to test new hard- and software concepts. With 24 dual-cores and 24 routers, arrayed in a 6x4 2D mesh, the cluster-on-a-chip was almost simultaneously presented to the public in the cosmopolitan cities of San Francisco, Peking and Braunschweig. To this end, Joe Schutz, vice-president of Intel’s worldwide research labs, arrived in the research metropolis of Lower Saxony.
After all, Intel’s lab there – in collaboration with its research facilities in Bangalore/India and Hillsboro/Oregon – is responsible for the design of the chip manufactured using the 45nm process. It was also there that the chip had earlier been emulated in FPGAs for a fairly long time and was first booted a few months ago. Now it’s being thoroughly validated. As it’s an experimental chip, it offers numerous configuration options for the memory controllers, the routers and the cores – many more than production chips usually do. With 567mm² it’s around the same size as a POWER7, about double the size of a Nehalem quad-core. But with 1.3 billion transistors, it’s a little less densely packed.
In contrast to the former test chip, the 80-core tera-scale processor (code-named Poseidon), which was composed of single ALU-like cores, the Rock Creek is fitted with complete x86 cores, similar to the Pentium 55C, but unlike the Larrabee limited to 32 bits. Another difference between the Larrabee and the Rock Creek is that the latter’s cores can each run their own OS. Right now, that’s an adapted Linux OS but Microsoft is also very dedicated and provides tools. If it’s possible to make Windows run on the SCC is still unclear, but anyway, the researchers at Microsoft have various other operating systems up their sleeves.
Tiny Tiles
Each SSC core has its own L1 cache as well as a L2 cache of 256KB; every two cores share a router and a 16KB message buffer. All together make up a so called “tile”. For every six tiles, a DDR3 memory controller is provided.
The communication between the cores is realized via messages, as is common for clusters. The traditional shared memory model of the SMP systems has the disadvantage that, with an increasing core number, the overhead gets bigger and bigger because of the cache consistency protocol and the system is slowed down more and more. On the other hand, models based on messages have proved their worth for larger ensembles; they scale up to hundreds and thousands of cores. However, additional mechanisms, like software-controlled adaptive cache consistency, can simulate SMP systems. Further, the message buffers are together organized as a shared memory of 384KB, which allows for very fast communication.
Each single tile can run with a different clock speed and the six banks of every four tiles can work with different voltages. Altogether, it adds up to 24 different voltage domains (also called “isles”). Additionally, there is a voltage- and frequency control for the memory controllers and the I/O network. This way, the 48 dual-cores only consume between 25 and 125 watts. Joe Schutz didn’t want to disclose any information concerning clock speed, performance or other further details, however. Those are reserved for the ISSCC – which doesn’t (yet) stand for “Intel Specific Single-chip Cloud Computer” but rather for “International Solid-State Circuit Conference”. The ISSCC will take place in San Francisco in February 2010 and should, of course, still offer some undisclosed highlights.
On the same occasion, AMD is going to present information about another highlight, the new x64 cores, manufactured using the 32nm SOI process, that are supposed to feature Zero-Power-Gates, which means that they can almost completely shut down unused cores – as is already the case with Intel’s Nehalem in its C6 state. According to an ISSCC advance notice, the AMD core features more than 35 million transistors (without the L2 cache), measures 9.69mm², manages over 3GHz of clock speed and consumes between 2.5 and 25 watts of power. If these specifications refer to the cores Bulldozer and Llano, which had been announced by AMD earlier, is everyone’s guess.
New Brooms
Intel has amicably settled its differences with AMD, but the investigation for market abuse in Europe continues regardless. Meanwhile, the European ombudsman Diamandouros has officially published his statement, which in part had already been blazoned out by the Wall Street Journal in summer. In deed, Diamandouros criticized the poor administrative practice of the commission with the argument that it had failed to properly document a meeting with the computer manufacturer Dell, which was related to the Intel investigation. He didn’t, however, comment on the question whether the commission infringed upon Intel’s right of defense.
Anyway, future anti-trust investigations are to be better documented; something that will scarcely affect the Dutch commissioner for competition Neelie Kroes, who has been on the job for many years and is known as a hardliner. In January 2010, she’ll become the commissioner for Information Society & Media and will – among other things – lead the European Network and Information Security Agency. Nonetheless, she will probably still have a say in the decision concerning Oracle’s acquisition of Sun before her designated successor, the current commissioner for Economic & Financial Affairs Joaquín Almunia from Spain, will take over the role of the guardian of competition. However, if he’ll deal more kindly with Intel – concerning its former business practices – remains to be seen.
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